The rapid progress in miniaturization of integrated circuits (IC) is leading to denser and finer pitched chips with ever increasing performance. In order to enhance the performance of advanced ICs, the interconnect systems are gradually migrating from aluminum-based metallurgy to higher-conductivity and more electromigration-resistant copper. Of the several schemes proposed for fabricating copper interconnects, the most promising method appears to be the Damascene process. Using this method, the trenches and vias are patterned in blanket dielectrics, and then metal is deposited into the trenches and holes in one step, followed by chemical mechanical polishing (CMP) to remove the unwanted surface metal. This leaves the desired metal in the trenches and holes, and a planarized surface for subsequent metallization. During the CMP process, especially for the via holes, more than 99% of the deposited copper is removed, and this is a very wasteful and expensive process, which includes a high usage of consumables such as pads and slurry. Furthermore, the disposition of used materials is a very important environmental issue. Therefore it is highly desirable to accomplish the copper metallization without CMP.
One approach to the formation of copper vias and metal lines includes the electroless deposition of copper. Electroless deposition of copper is used in printed circuit boards to manufacture copper lines and through holes where the line and hole dimensions are in the several tens to hundreds of microns. The is, of course, much larger than the sub-micron design rules for integrated circuit fabrication on silicon wafers. In this approach, Palladium (Pd) is often used as the activated base metal for electroless copper plating. Several different groups have shown the success of the same. For example, an article published by Bhansali and D. K. Sood, entitled, “A novel technique for fabrication of metallic structure on polyimide by selective electroless copper plating using ion implantation,” Thin Solid Films, vol. 270, p. 489–492, 1995, successfully used palladium ion implantation into polyimide to seed an electroless plated copper film on the polyimide surface. An ion dose range of 1.5×1015 to 1.2×1017 ions/cm2 was used. They also reported on the successful use of copper implantation into silicon to seed the electroless plating using a dose range of 5×1014 to 6.4×1016 ions/cm2. (See, Bhansali, S. et al, “Selective electroless copper plating on silicon seeded by copper ion implantation”, Thin Solid Films, vol. 253, no. 1–2, p. 391–394, 1994). An article published by M.-H. Kiang, et al, entitled, “Pd/Si plasma immersion ion implantation for selective electroless copper plating on SiO2, Applied Physics Letters, vol. 60, no. 22, p. 2767–2769, 1992, demonstrated selective deposition of copper in SiO2 trenches using Pd/Si plasma immersion ion implantation and electroless copper plating. An article published by J.-Y. Zhang et al, entitled, “Investigations of photo-induced decomposition of palladium acetate for electroless copper plating”, Thin Solid Films, vol. 318, p. 234–238, 1998, illustrates photo-induced palladium decomposition of acetate performed by using argon and xenon excimer vacuum ultraviolet sources in the formation of palladium, which acted as a catalyst for subsequent copper plating by means of an electroless bath for selective copper deposition. An article published by M.-H. Bernier et al, entitled, “Laser processing of palladium for selective electroless copper plating”, SPIE Proc., vol. 2045, p. 330–337, 1993 demonstrated that the direct writing of palladium features by the Ar+ laser-induced pyrolytic decomposition of an organometallic palladium resins on polyimide and Si3N4 led to active Pd sites which were selectively copper plated. Also, as described in an article published by J.-L. Yeh et al, entitled, “Selective Copper Plating of Polysilicon surface Micromachined Structures”, Technical digest of 1998 Solid-State Sensor and Actuator Workshop, Transducer Research Foundation Catalog No. 98TRF-0001, p. 248–251, 1998, Yeh et al. exposed polycrystalline silicon structures to a palladium solution that selectively activated the polysilicon structure, but not the silicon oxide or nitride layers. Upon immersion into a copper plating solution at a temperature between 55 and 80° C., the copper nuclei were initially formed on the Pd+ activated polysilicon surface. After the formation of a thin-layer copper, copper started to deposit on this thin initiated copper film. Recently, an article published by V. M. Dubin et al, entitled, “Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration”, J. Electrochem. Soc., vol. 144, no. 3, p. 898–908, 1997, disclosed a novel seeding method for electroless copper deposition on sputtered copper films with an aluminum protection layer. This seeding method consisted of (I) deposition of Cu seed layer by sputtering or evaporation, (ii) deposition of a sacrificial thin aluminum layer without breaking vacuum, (iii) etching the aluminum layer in the electroless Cu plating bath, followed by electroless Cu deposition.
Here, Dubin et al. designed and constructed a single-wafer electroless copper deposition tool with up to 200 mm wafer capability, and an electroless copper deposition process was developed. Electroless Cu films deposited at high plating rate (up to 120 nm/min) in solutions with optimized plating chemical environment exhibited low resistivity (<2 μohm cm for as deposited films), low surface roughness, and good electrical uniformity.
All of these above described methods are rather complex which means that the number of process steps involved in integrated circuit fabrication increases. The problem associated with these methods is that an increase in the number of process steps makes integrated circuit fabrication more costly. Further, none of the above described methods address or provide a resolution to the costly excess expenditure of materials and the environmental concerns when such processes are implemented to form sub-micron vias and metal lines on wafers in a conventional CMP fabrication process.
For the reasons stated above and for others which will become apparent from reading the following disclosure, structures and methods are needed which alleviate the problems associated with via and metal line fabrication processes. These structures and methods for via and metal line fabrication must be streamlined and accommodate the demand for higher performance in integrated circuits even as the fabrication design rules shrink.